1. Field of the Invention
The present invention relates to MIS (metal insulator semiconductor) transistors and particularly to an MIS transistor having an LDD (lightly doped drain) structure and a method of manufacturing thereof.
2. Description of the Prior Art
In order to accomplish large scale integration and high reliability of semiconductor apparatus, it is indispensably necessary to reduce semiconductor devices of a semiconductor apparatus to microscopic sizes or to enhance performance thereof. A typical example of a semiconductor device is a MOS (metal oxide semiconductor) transistor as shown in FIG. 32. Referring to FIG. 32, a MOS transistor 1 comprises a gate electrode 4 of polysilicon or the like through a thin gate oxide film 3 on a surface of a silicon substrate 2. A pair of source and drain regions 5 and 6 are formed spaced from each other on the surface of the silicon substrate 2 with a gate electrode 4 being provided therebetween. A surface region of the silicon substrate 2 located between the source and drain regions 5 and 6 constitutes a channel region 7 of the MOS transistor 1.
The size of the MOS transistor 1 is reduced according to a scaling rule in order to realize a miniaturized structure without deteriorating the electric characteristics of the transistor. Thus, in this structure, a gate length of the gate electrode 4 or a channel length of the channel region 7 for example is reduced. However, this reduction of the structure involves a problem of a short channel effect which does not occur conspicuously in the prior art. More specifically, the reduction of the channel length causes concentration of an electric field near the drain region 6, resulting in deterioration of dielectric strength of the drain region. In addition, hot carriers generated by the concentration of electric field penetrate into the gate oxide films 3 and part of them are trapped or cause an interfacial potential. As a result, characteristic deteriorations such as a change of a threshold voltage V.sub.TH or lowering of mutual conductance gm occur.
In order to solve such difficulties due to concentration of electric field obstructing fine reduction of a device structure, MOS transistors of an LDD structure have been proposed. FIG. 33 shows a structure of such an LDD MOS transistor. This structure of the LDD MOS transistor is shown for example in "Fabrication of High-Performance LDD FETs with Oxide Sidewall-Spacer Technology" by P. J. Tsang, IEEE Transaction on Electron Devices, Vol. ED-29 1982. Referring to FIG. 33, the LDD MOS transistor has a double offset structure in which source and drain regions 5 and 6 include high-concentration n.sup.+ impurity regions 5a and 6a and low-concentration n.sup.- impurity regions 5b and 6b, respectively. This LDD structure is adopted particularly for the purpose of suppressing electric field concentration near the drain region 6. The n.sup.- impurity regions 5b and 6b are formed on side surfaces of the source and drain regions 5a and 6a, respectively, so that impurity concentrations in pn junction portions with the substrate may be changed gradually. Thus, a depletion layer generated during operation of the transistor extends toward the source and drain regions to attenuate electric field. The above described structure prevents breakdown between the drain region 6 and the channel region 7 and thus prevents deterioration of dielectric strength of the drain region 6. Further, the attenuation of electric field concentration serves to suppress generation of hot carriers. However, in the above described LDD structure, another problem occurs that an on-resistance characteristic of the transistor is deteriorated. The low-concentration n.sup.- impurity regions 5b and 6b of the source and drain regions function as high-resistance regions because of the low impurity concentration. Consequently, the n.sup.- impurity regions 5b and 6b become parasitic resistances connected in series between the source and drain regions 5 and 6, causing lowering of drain current and deterioration of the on-resistance characteristic of the transistor.
Further, the influence of the parasitic resistance is strengthened by the structure in which the sidewalls 8 of the silicon oxide films are formed on the surfaces of the low-concentration n.sup.- source and drain regions 5b and 6b. More specifically, hot carriers having larger energy than that in a thermal equilibrium state are generated due to the electric field near the drain region 6. Those hot carriers are generated near the n.sup.- impurity region 6b of the drain region and some of them are injected in a lower portion of the sidewall 8 of the drain region. A surface region near the n.sup.- impurity region 6b is depleted with time due to an electric field caused by the hot carriers trapped at an energy level in the underlying oxide film of the sidewall 8. As a result, the threshold voltage V.sub.TH of the transistor is raised or conductance is decreased due to the depleted high-resistance portion of the n.sup.- impurity region 6b even in an operation state. Consequently, the drain characteristics are deteriorated and duration of reliability of the transistor practically utilizable is shortened.
Therefore, in order to prevent influence of hot carriers trapped in the sidewalls of the gate electrode, a transistor structure as shown in FIG. 34 has been proposed. This structure is the so-called gate overlapped LDD structure, in which a gate electrode is formed to overlap low-concentration impurity regions of the LDD structure. The structure of FIG. 34 is indicated in Japanese Patent Laying-Open No. 119078/1986. A transistor of a similar structure is disclosed in "The Impact of Gate-Drain Overlapped LDD (Gold) for Deep Submicron VLSI's", by R. Izawa, Technical Digest of International Electron Devices Meeting, pp. 38, 1987 or in U.S. Pat. No. 4,727,038.
As shown in FIG. 34, in a gate overlapped LDD MOS transistor, low-concentration n.sup.- impurity regions 5b and 6b of source and drain regions 5 and 6 are formed on a surface of a silicon substrate 2 under regions of a gate electrode 4. In such a gate electrode structure, if hot carriers generated near the drain 6 are injected into a gate oxide film 3, those hot carriers can be removed under the influence of electric field from the gate electrode 4. Consequently, the surfaces of the n.sup.- impurity regions 5b and 6b can be prevented from being depleted and having high resistance. Further, change in a threshold voltage and deterioration of mutual conductance can be prevented.
However, in such a gate overlapped LDD MOS transistor, a gate capacitance is increased by an amount corresponding to extended regions of the gate electrode 4 compared with the LDD MOS transistor shown in FIG. 33. In other words, the capacitance portion formed by the gate electrode 4 over the n.sup.- impurity regions 5b and 6b, the gate oxide film 3 and the silicon substrate 2 causes the increase of the gate capacitance. As the result, responsiveness as the MOS transistor is lowered.
In a gate overlapped type of LDD MOS transistor, in some cases, boundary portions between n.sup.+ impurity regions 5a, 6a and n.sup.- impurity regions 5b and 6b are diffused under the gate electrode 4 by a thermal process of the manufacturing processes. In this case, regions where the end portions of the gate electrode 4 and the n.sup.+ impurity regions 5a and 6a are overlapped are formed. When thickness of the gate oxidization layer 3 becomes thin in such an overlapped region, tunneling occurs between the bands in a depleted drain region, whereby drain leak current is generated. Such a phenomenon is described in "IEDM Technical Digest", by T. Y. Chan, J. Chen, P. K. Ko and C. Hu, 1987.
As described in the foregoing, in conventional LDD MIS transistors, n.sup.- impurity regions become parasitic resistance due to hot carriers and gate capacitance generated in a gate overlapped type of LDD structure is increased or a drain leak current is generated.